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features ? digital self-supervising watchdog with hysteresis three 250-ma output drivers one relay driver, two lamp drivers lamp drivers with auxiliary ground short-circuit-protected lamp drivers lamp drivers with status feedback enable output overvoltage/undervoltage detection and reset all power outputs protected against standard transients all power outputs protected against 40v load dump lamp drivers automatically activated if v s is disconnected lamp drivers automatically acti vated via aux gnd if standard ground is disconnected 1. description the ATA6809 is designed to su pport the fail-safe function of safety-critical systems such as abs. it includes a relay driver, two independent short-circuit-protected lamp drivers which are supplied by redundant grou nd lines, two monitoring circuits for the lamp driver output voltage and output current, a watchdog controlled by an external rc network, and a reset circuit initiated by an overvoltage or undervoltage condition of the 5v supply providing a positive and a negative reset signal. fail-safe ic with relay driver and lamp driver ATA6809 rev. 4902a?auto?11/05
2 4902a?auto?11/05 ATA6809 figure 1-1. block diagram 2. pin configuration figure 2-1. pinning so20 digital input lamp 1 digital input relay digital input lamp 2 digital input wd feedback lamp 1 feedback lamp 2 debouncing of over- and under- voltage detection short-circuit detection and temperature monitor oscillator monitoring rc-oscillator watchdog p reset n reset logic open-collector 250 ma lamp driver 1 temperature open-collector 250 ma lamp driver 2 open-collector 250 ma relay driver open-collector 25 ma enable driver la1i la2i reli wdi fbla1 fbla2 pres nres micro- controller osc gnd aux gnd la1o la2o relo eno vs loads 1 2 3 4 5 6 7 8 10 9 19 18 17 16 14 15 13 12 11 20 relo gnd gnd fbla1 nres pres la1i la2i gnd gnd gnd la2o aux gnd eno vs la1o fbla2 osc rel1 wdi ATA6809
3 4902a?auto?11/05 ATA6809 table 2-1. pin description pin name type function logic 1 reli digital input activation of relay driver driver on: l driver off: h 2 la1i digital input activation of lamp driver 1 driver off: l driver on: h 3 la2i digital input activation of lamp driver 2 driver off: l driver on: h 4 relo open-collector driver output fail-safe relay driver driver off:--- driver on: l 5, 6 gnd supply standard ground 7 fbla1 digital output feedback lamp 1 see table 3-1 on page 5 and table 3-2 on page 5 8 nres digital output negative reset signal reset: l no reset: h 9 pres digital output positive reset signal reset: h no reset: l 10 fbla2 digital output feedback lamp 2 see table 3-1 on page 5 and table 3-2 on page 5 11 osc analog input external rc for watchdog timer 12 eno open-collector output watchdog disable output watchdog ok: --- watchdog not ok: l 13 aux, gnd supply auxiliary ground of lamp drivers 14 la2o open-collector driver output warning lamp driver driver off: --- driver on: l 15, 16, 17 gnd supply standard ground 18 la1o open-collector driver output warning lamp driver driver off: --- driver on: l 19 vs supply 5v supply 20 wdi digital input watchdog trigger signal pulse sequence
4 4902a?auto?11/05 ATA6809 3. detailed block diagram with external components figure 3-1. detailed block diagram + - v ref 4 + - v ref 5 + - + - + - oscillator watchdog + - v ref 1 failure detection lamp 1 + - + - + - + - v ref2 v ref3 19 14 gnd 15 13 vs reli osc + pres temperature shut down a c ground backup aux gnd gnd integrated oscillator internal timing short-circuit protection d b d c v s v batt v batt push pull r- push pull r+ reset delay push pull l1 failure detection lamp 2 push pull l2 a d v s v s b c e v ref2 e e reset debouncing 1 2 3 20 11 la1i la2i wdi 18 7 4 8 9 10 12 - nres relo v batt fbla1 la1o la2o fbla2 eno 5 6 16 17 aux gnd v ref3 d e b o u n c i n g d e b o u n c i n g
5 4902a?auto?11/05 ATA6809 note: lamp voltage is logic 1 if output voltage > threshold voltage detection lamp voltage is logic 0 if output voltage < threshold voltage detection lamp current is logic 1 if output current > threshold current detection lamp current is logic 0 if output current < threshold current detection table 3-1. truth table for lamp drivers and lamp feedback inputs outputs comment lamp (i) lamp voltag e lamp current lamp driver current lamp current feedback lamp 010offoff 1 output ok or open (internal pull-up) or shorted to v batt 0 1 1 on off 1 output shorted to v batt and faulty input level 0 0 1 on on 0 internal driver activated due to internal failure 0 0 0 off on 0 output shorted to gnd 1 0 1 on on 0 output ok 1 1 1 on off 1 output shorted to v batt 110offoff 1 internal driver deactivated due to internal failure or thermal shutdown 1 0 0 off on/off 1 output shorted to gnd or open table 3-2. table of fault detection condition feedback lamp lamp input is 0 (lamp off) lamp input is 1 (lamp on) normal operation 1 0 lamp output shorted to gnd 0 (= detection) 1 (= detection) lamp output shorted to v batt 1 (= no detection) 1 (= detection) lamp output open 1 (= no detection) 1 (= detection) feedback shorted to gnd 0 (= detection) 0 (= no detection) feedback shorted to v s 1 (= no detection) 1 (= detection) lamp input shorted to gnd 1 (= no detection) 1 (= detection) lamp input shorted to v s 0 (= detection) 0 (= no detection)
6 4902a?auto?11/05 ATA6809 4. fail-safe functions a fail-safe ic has to maintain its monitoring function even if there is a fault condition at one of the pins (for example, a short circuit). this ensures that a microcontroller system is not brought into a critical status. a critical status is reached if the system is not able to actuate a warning lamp and switch off the relay. the following table shows fault conditions for different pins during which the ic still works as a fail-safe device. 5. description of the watchdog 5.1 abstract the microcontroller is monit ored by a digital window watchdog which accepts an incoming trig- ger signal of a constant frequency for correct oper ation. the frequency of the trigger signal can be varied in a broad range as the watchdog's time window is determined by external rc components. the following description refers to figure 1-1 on page 2 . figure 5-1. watchdog block diagram table 4-1. table of fault condition pin function short to v s short to v batt short to gnd open circuit la2o short-circuit proof driver for warning lamp la2o partly on la2o off la2o on la2o off la2i digital input to activate warning lamp la2o on la2o on la2o off la2o on fbla2 digital feedback of warning lamp faulty feedback faulty feedback faulty feedback faulty feedback la1o short-circuit proof driver for warning lamp la1o partly on la1o off la1o on la1o off la1i digital input to activate warning lamp la1o on la1o on la1o off la1o on fbla1 digital feedback of warning lamp faulty feedback faulty feedback faulty feedback faulty feedback reli digital input to activate the fail safe relay relay off relay off relay on relay off wdi watchdog trigger input watchdog reset wat chdog reset watchdog reset watchdog reset osc capacitor and resistor of watchdog watchdog reset watchdog reset watchdog reset watchdog reset slope detector up/down counter dual mux binary counter rs-ff rcosc wdi reset oscerr wd-ok
7 4902a?auto?11/05 ATA6809 5.2 wdi input (pin 20) the microcontroller has to provide a trigger signal with the frequency f wdi , which is fed to the wdi input. a positive edge of f wdi detected by a slope detector resets the binary counter and also clocks the up/down counter. the up/down coun ter only counts from 0 to 3 or reverse. each correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. as soon as the counter reaches the count of 3 the rs flip-flop is set (see figure 5-2 ). a missing incoming trigger signal is det ected after 250 clocks of the internal watchdog frequency f rc (see ?wd-ok output? ) and resets the up/down counter directly. 5.3 rcosc input the ic generates a time base (frequency f rc ) independent from the microcontroller via external rc circuitry. the watchdog's time window refers to a frequency of rc = 100 f wdi 5.4 reset input during power-on and undervoltage/overvoltage detection, a reset signal is fed to this pin. it resets the watchdog timer and sets the initial state. 5.5 wd-ok output after the up/down counter has reached 3 (see the wd state diagram, figure 5-2 on page 7 ), the rs flip-flop is set and the wd-ok output becomes logic 1. this information is available for the microcontroller at the open-collector output eno. if, on the other hand, the up/down counter is decremented to 0, the rs flip-flop is reset, and the wd-ok output and the eno output are dis- abled. the wd-ok output also controls a dual mu x stage which shifts the time window by one clock after a successful trigger, thus forming a hysteresis to provide stable conditions for the evaluation of the trigger signal "good? or ?bad". the wd-ok signal is also reset if the watchdog counter is not reset after 250 clocks (missing trigger signal). 5.6 watchdog state diagram figure 5-2. watchdog state diagram in each block, the number represents the state of the counter. ?f? or ?nf? indicates the fault sta- tus of the counter. fault status is indicated by "f " and no-fault status is indicated by "nf". when the watchdog is powered up initially, the counter starts at the 0/f block (initial state). "good" indi- cates that a pulse has been received whose wi dth resides within t he timing window. "bad" indicates that a pulse has been received whose width is either too short or too long. 1/nf 2/nf o/f 1/f 2/f 3/nf bad good bad good bad good good bad good good bad bad initial status
8 4902a?auto?11/05 ATA6809 5.7 watchdog window calculation example with recommended values c osc = 3.3 nf (should preferably be 10%, npo) r osc = 39 k ? (may be 5%, r osc < 100 k ? due to leakage current and humidity) 5.8 rc oscillator t wdc (s) = 10 ? 3 [c osc (nf) [(0.00078 r osc (k ? )) + 0.0005]] f wdc (hz) = 1 / (t wdc ) 5.9 watchdog wdi f wdi (hz) = 0.01 f wdc t wdc = 100 s -> f wdc = 10 khz f wdi = 100hz -> t wdi = 10 ms 5.9.1 wdi pulse width for fault detection after 3 pulses upper watchdog window minimum: 169 / f wdc = 16.9 ms -> f wdc / 169 = 59.1hz maximum: 170 / f wdc = 17.0 ms -> f wdc / 170 = 58.8hz lower watchdog window minimum: 79 / f wdc = 7.9 ms -> f wdc / 79 = 126.6hz maximum: 80 / f wdc = 8.0 ms -> f wdc / 80 = 125.0hz 5.9.2 wdi dropouts for immediate fault detection minimum: 250 / f wdc = 25 ms maximum: 251 / f wdc = 25.1 ms 5.9.3 remark to reset delay the duration of the overvoltage or undervoltage pulse determines the enable and reset output. a pulse duration shorter than the debounce time has no effect on the outputs. a pulse longer than the debounce time results in the first reset delay. if a pulse appears during this delay, a 2nd delay time is triggered. therefore, the total reset delay time can be longer than specified in the datasheet. figure 5-3. watchdog timing diagram with tolerances time/s 79 / f wdc 80 / f wdc 169 / f wdc 170 / f wdc 250 / f wdc 251 / f wdc watchdog window update rate is good update rate is too fast update rate is either too fast or good update rate is either too slow or good update rate is too slow update rate is either too slow or pulse has dropped out pulse has dropped out
9 4902a?auto?11/05 ATA6809 6. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol value unit supply voltage range v s ?0.2 to +16 v aux gnd offset voltage to gnd v aux 1.5 v aux gnd offset current to gnd i aux ?600 ma power dissipation v s = 5v; t amb = 125 c p tot 700 mw thermal resistance r thjc 25 k/w junction temperature t j 150 c ambient temperature range t amb ?40 to +125 c storage temperature range t stg ?55 to +155 c 7. electrical characteristics v s = 5v, t amb = ?40 to +125c; reference pin is gnd; f intern = 100 khz + 50% ? 45%, f wdc = 10 khz 10%; f wdi = 100hz parameters test conditions symbol min. typ. max. unit supply voltage operation range general v s 4.5 5.5 v operation range reset v s 1.5 16.0 v supply current lamp driver on, relay off t amb = ?40 c t amb = 125 c 40 35 ma ma lamp driver off, relay on t amb = ?40 c t amb = 125 c 25 20 ma ma lamp driver off, relay off t amb = ?40 c t amb = 125 c 15 10 ma ma auxiliary ground (aux gnd) aux gnd offset voltage operation range t amb = ?40 c t amb = 90 c t amb = 125 c ?1.2 ?0.65 ?0.5 1.2 1.0 0.8 v v v aux gnd offset voltage to gnd i aux = ?600 ma ?1.7 3.0 v digital inputs (la1i, la2i, rel1 and wdi) detection low ?0.2 0.2 v s v detection high 0.7 v s v s + 0.5v v resistance to v s 10 40 k ? input current low input voltage = 0v 100 550 a input current high input voltage = v s ?5 5 a
10 4902a?auto?11/05 ATA6809 digital outputs; lamp dri ver feedbacks (fbla1, fbla2) voltage low i 1.6 ma 0 0.5 v voltage high i 10a 10a i 1.6 ma 0.8 v s 0.7 v s + 0.1 v s v threshold voltage detection 0.4 v s 0.5 v s v threshold current detection 10 50 ma digital outputs (pres and nres) voltage high i 100a 0.7 v s + 0.1 v s v voltage low i 1 ma 0 0.3 v digital output (eno) with open collector saturation voltage low i 25 ma 0 0.3 v clamping voltage 26 30 v current limit low 25 ma leakage current v eno = 5v v eno = 16v v eno = 26v 20 100 200 a a a lamp drivers (la1o and la2o) wi th integrated pull-up resistor saturation voltage i 125 ma; v s = 5v i 125 ma; v s = 0v 0.5 1.5 v v saturation voltage 250 ma requires enhanced heat sink i 250 ma; v s = 5v i 250 ma; v s = 0v i 250 ma; no gnd 1.0 2.0 3.0 v v v maximum load current t amb = 90 c t amb = 125 c 250 180 ma ma clamping voltage 26 30 v leakage current v la1o, la2o = 16v v la1o, la2o = 26v 1 3 ma ma threshold current limitation 0.5 1.0 a pull-up resistor 2 17 k ? relay driver (relo) saturation voltage i 250 ma 0.5 v maximum load current t amb = 90 c t amb = 125 c 250 200 ma ma clamping voltage 26 30 v leakage current v batt = 16v v batt = 26v 20 200 a a 7. electrical characteristics (continued) v s = 5v, t amb = ?40 to +125c; reference pin is gnd; f intern = 100 khz + 50% ? 45%, f wdc = 10 khz 10%; f wdi = 100hz parameters test conditions symbol min. typ. max. unit
11 4902a?auto?11/05 ATA6809 reset and v s control lower reset level v s 4.5 4.8 v upper reset level v s 5.2 5.5 v hysteresis 25 mv reset debounce time 120 500 s reset delay 20 80 ms watchdog timing feedback reaction time (fbla1, fbla2) no fault, edge at la1i, la2i t fb 2.56 12.8 ms minimum lamp input toggle time for a secure feedback reaction no fault, pulse at la1i, la2i t p, f b 10.24 ms power-on-reset prolongation time t por 34.3 103.1 ms detection time for rc-oscillator fault v rc = constant t rcerror 81.9 246 ms time interval for overvoltage/ undervoltage detection t d,ouv 0.16 0.64 ms reaction time of nres output on overvoltage/undervoltage t r,ouv 0.187 0.72 ms minimum toggle time for a secure broken ground detection t p, b g n d 13.3 s maximum reaction time for broken ground detection t r,bgnd 100 s nominal frequency for wdi f rc = 100 f wdi f wdi 10 130 hz nominal frequency for rc f wdi = 1 / 100 f rc f rc 113khz minimum pulse duration for a secure wdi input pulse detection t p, w d i 182 s frequency range for a correct wdi signal f wdi 64.7 112.5 hz number of incorrect wdi trigger counts for locking the outputs n lock 3 number of correct wdi trigger counts for releasing the outputs n release 3 detection time for a stuck wdi signal v wdi = constant t wdierror 24.5 25.5 ms watchdog timing relative to f rc minimum pulse duration for a securely wdi input pulse detection 2 cycles frequency range for a correct wdi signal 80 170 cycles hysteresis range at the wdi ok margins 1 cycle detection time for a stuck wdi signal v wdi = constant 250 251 cycles 7. electrical characteristics (continued) v s = 5v, t amb = ?40 to +125c; reference pin is gnd; f intern = 100 khz + 50% ? 45%, f wdc = 10 khz 10%; f wdi = 100hz parameters test conditions symbol min. typ. max. unit
12 4902a?auto?11/05 ATA6809 note: 1. lamp drivers: 1.2 ? lamps need to be added to the source resistance. relay driver: relay coil with r min = 70 ? need to be added to the source resistance. 7.1 application hints a.) the lamp output pins la1o and la2o may need to be protected by external protection diodes (for ex ample, bav 202) against re versed battery, in order to avoid a reset during negative pulses. b.) if pilot lamps with a wattage of p > 1.2w are connected, external zener diodes are mandatory. 8. timing diagrams figure 8-1. watchdog in too fast condition table 7-1. protection against transient voltages according to iso tr 7637-3 level 4 (except pulse 5) pulse voltage source resistance (1) rise time duration amount 1 ?110v 10 ? 100v/s 2 ms 15.000 2 +110v 10 ? 100v/s 0.05 ms 15.000 3a ?160v 50 ? 30v/ns 0.1s 1h 3b +150v 50 ? 20v/ns 0.1s 1h 5 40v 2 ? 10v/ms 250 ms 20 wdi too fast normal operation normal operation 5 v 0 v wdi 0 v relo 5 v 0 v eno v batt 0 v laxo don't care v batt
13 4902a?auto?11/05 ATA6809 figure 8-2. watchdog in too slow condition figure 8-3. overvoltage condition normal operation 5 v 0 v wdi wdi too low normal operation 0 v relo 5 v 0 v eno v batt 0 v laxo don't care v batt 0 v v s 5 v v batt 0 v relo 5 v 0 v eno 5 v 0 v nres v batt 0 v laxo don't care reset debounce time 3 good wdi pulses 1st reset delay 2nd reset delay 5.5 v > 120 s < 120 s overvoltage condition 5.5 v
14 4902a?auto?11/05 ATA6809 figure 8-4. undervoltage condition 0 v v s 5 v v batt 0 v relo 5 v 0 v eno 5 v 0 v nres v batt 0 v laxo don't care reset debounce time 3 good wdi pulses 1st reset delay 2nd reset delay > 120 s < 120 s undervoltage condition 4.5 v 4.5 v
15 4902a?auto?11/05 ATA6809 10. package information 9. ordering information extended type number package remarks ATA6809-tgqy so20 special lead frame taped and reeled, pb-free technical drawings according to din specifications package so20 dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 110
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